1. Field of the Invention
The present invention relates to a metal insulator semiconductor (MIS) type semiconductor device.
2. Description of the Related Art
In the conventional semiconductor devices having a MIS structure, it is a common practice to form all of the source, drain and channel in a semiconductor substrate (see, for example, Japanese Unexamined Patent Publication (Kokai) No. 61-63049), or in the case of the formation of a transistor structure in a semiconductor layer grown on an insulating film, it is a common practice to form all of the source, drain and channel in the grown semiconductor layer (see, for example, Japanese Unexamined Patent Publication (Kokai) No. 62-104173).
In the above-described conventional semiconductor devices having a MIS structure, when all of the source, drain and channel are formed in a semiconductor substrate, it is necessary to form diffusion layers as the source and drain. In this case, since the lateral diffusion in the diffusion layer should be taken into consideration, it is difficult to reduce the channel length, and this inhibits a high-density integration. Further, when a complementary circuit is formed through the use of an element wherein the source, drain and channel all are formed in a semiconductor substrate, the device may be damaged due to the formation of a parasitic element.
On the other hand, when the source, drain and channel all are formed in a semiconductor layer on an insulating film, although a switching operation is possible, of the quality of the semiconductor layer is released and thus a leakage current exists in the off state.